CHARACTERIZATION, MODELLING AND SIMULATION OF SUB-45NM SOI DEVICES

被引：0

作者：

Rodriguez, Noel ^{[1
]}

Gamiz, Francisco ^{[1
]}

Cristoloveanu, Sorin ^{[2
]}

机构：

[1] Univ Granada, Dept Elect & Tecnol Comp, E-18071 Granada, Spain

[2] MINATEC, Inst Microelect Elect & Photon IMEP LACH, F-3800 Grenoble, France

来源：

CAS: 2009 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, PROCEEDINGS | 2009年

关键词：

INSULATOR INVERSION-LAYERS; MONTE-CARLO; EXTRACTION; OPERATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The silicon CMOS technology is evolving following aggressive scaling rules which lead to severe physical limits. Different solutions have been proposed during the last years to bypass these limitations. Among others, ultrathin-body and BOX (UTB2) Silicon-On-Insulator technology has been shown to provide excellent scalability properties beyond the 22nm node. The existing models for characterization, modelling and simulation of ultrathin SOI devices must be revisited from the wafer level to the transistor level. In this paper we review our recent results on SOI wafer characterization, SOI transistors characterization and SOI-transistors simulation. All these results update and highlight the possibilities of SOI technology.

引用

页码：57 / +

页数：3

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