Fault-tolerant 3D Mesh for Network-an-Chip

One of the crucial aspects in designing Network-onChip (NoC) is to ensure reliability, which is little explored for 3D NoCs in the literature till now. Therefore, in this paper, we investigate a novel fault-tolerant design for 3D NoCs that can go beyond existing fault-tolerant designs that are mostly applicable for 2D NoCs. In our design, we propose to divide a 3D NoC into 2 x 2 x 2 sub-networks or blocks. Then, we place four spare routers at the centers of four different planes. Here, we propose sparing of routers considering the fact that routers incur much lower cost compared to that of main processing elements such as processor. Later, we formulate separate mathematical models pertinent to our proposed design along with two benchmark designs. Subsequently, based on the models, we simulate performances of our proposed design along with the benchmark ones in terms of reliability and mean time to failure (MTTF). Simulation results demonstrate that our proposed design can enhance fault tolerance of 3D NoCs by significant margins compared to that of existing benchmark designs.