Power and Area Evaluation of a Fault-Tolerant Network-on-Chip

被引：0

作者：

Kadeed, Thawra ^{[1
]}

Rambo, Eberle A. ^{[1
]}

Ernst, Rolf ^{[1
]}

机构：

[1] TU Braunschweig, Inst Comp & Network Engn, Braunschweig, Germany

来源：

2017 30TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | 2017年

关键词：

ASIC; Realistic Power Calculation; Resilient NoC; Power Analysis under Errors;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation as well as under errors. Experiments show that the employed error detection and retransmission schemes in our NoC contribute low power overhead when compared to previously proposed scheme.

引用

页码：190 / 195

页数：6

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