A New Current-Integrating Bang-Bang Phase Detector for Clock and Data Recovery

被引：1
|
作者：
Yuan, Fei [1 ]
机构：
[1] Ryerson Univ, Dept Elect & Comp Engn, Toronto, ON, Canada
来源：
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2008年
关键词：
D O I：
10.1109/MWSCAS.2008.4616945
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a new current-integrating bang-bang phase detector that is insensitive to data transient disturbances. The phase detector extracts early-late phase information between the input and retimed data by integrating the input data and its complementary on two identical capacitors. In addition, it employs only one regenerative DFF for phase detection, significantly lowering hardware cost. The phase detector has been implemented in TSMC-0.18 mu m 1.8V CMOS technology and analyzed using Spectre-RF from Cadence Design Systems with BSIM3.3v device models. Simulation results are presented.
引用
收藏
页码：898 / 901
页数：4
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