Cloud-based Evolutionary Algorithm for Network on Chip (NoC) Test Scheduling using NoC as TAMs

被引：0

作者：

Xu, Chuanpei ^{[1
]}

Chrzanowska-Jeske, Malgorzata ^{[2
]}

Zhang, Pu ^{[3
]}

Hu, Cong ^{[1
]}

机构：

[1] Guilin Univ Elect Technol, Guilin 541004, Peoples R China

[2] Portland State Univ, Portland, OR 97201 USA

[3] Mil Representat Off Wuhan Bur Stationed, Changsha 410014, Peoples R China

来源：

EIGHTH INTERNATIONAL SYMPOSIUM ON PRECISION ENGINEERING MEASUREMENTS AND INSTRUMENTATION | 2013年 / 8759卷

关键词：

network on chip; test; optimization; cloud evolution algorithm;

D O I：

10.1117/12.2016961

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

fNetwork on Chip is a novel system-on-chip paradigm. Developing an efficient test strategy is essential for future NoC development. We propose to use cloud theory to solve core test scheduling problem for NoC using NoC communication network as test access mechanisms (TAMs). A cloud model is build and used by our evolutionary algorithm to optimize NoC testing time under power consumption constraint. The goal is to use cloud evolutionary algorithm to schedule testing of NoC cores as much in parallel as possible. Experiments show that the proposed algorithm converges much faster than the tradition evolutionary algorithm and can find testing schedules that reduce NoC testing time.

引用

页数：8

共 50 条

[31] An Address Remapping Algorithm to Reduce Power Consumption in NoC-based Chip-Multiprocessors
Chen, Shuyu
Huang, Letian
Li, Song
[J]. 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2016, : 209 - 210
[32] TRANSITION LEVEL ENERGY CONSUMPTION OF NOC (Network-On-Chip)USING DATA ENCODING TECHNIQUES
Ashokkumar, N.
Kavitha, A.
[J]. 2015 2ND INTERNATIONAL CONFERENCE ON COMPUTING FOR SUSTAINABLE GLOBAL DEVELOPMENT (INDIACOM), 2015, : 1690 - 1693
[33] On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
Zhang, Xiao
Kerkhoff, Hans G.
Vermeulen, Bart
[J]. 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 531 - 537
[34] Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication
Kumar, Adesh
Sharma, Paawan
Gupta, Mukul Kumar
Kumar, Roushan
[J]. WIRELESS PERSONAL COMMUNICATIONS, 2018, 102 (03) : 2211 - 2231
[35] A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures
Qian, Zhi-Liang
Juan, Da-Cheng
Bogdan, Paul
Tsui, Chi-Ying
Marculescu, Diana
Marculescu, Radu
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (03) : 471 - 484
[36] A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems
Bhojwani, P
Mahapatra, R
Kim, EJ
Chen, T
[J]. 18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 124 - 129
[37] Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication
Adesh Kumar
Paawan Sharma
Mukul Kumar Gupta
Roushan Kumar
[J]. Wireless Personal Communications, 2018, 102 : 2211 - 2231
[38] An Efficient Network-on-Chip (NoC) based Multicore Platform for Hierarchical Parallel Genetic Algorithms
Xue, Yuankun
Qian, Zhiliang
Wei, Guopeng
Bogdan, Paul
Tsui, Chi-Ying
Marculescu, Radu
[J]. 2014 EIGHTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2014, : 17 - 24
[39] Core-based SoC test scheduling using evolutionary algorithm
Xia, Y
Chrzanowska-Jeske, M
Wang, B
[J]. CEC: 2003 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-4, PROCEEDINGS, 2003, : 1716 - 1723
[40] Dynamic workflow scheduling in the cloud using a neural network-based multi-objective evolutionary algorithm
Naik, K. Jairam
Chandra, Siddharth
Agarwal, Paras
[J]. INTERNATIONAL JOURNAL OF COMMUNICATION NETWORKS AND DISTRIBUTED SYSTEMS, 2021, 27 (04) : 424 - 451

← 1 2 3 4 5 →