A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems

被引：7
|
作者：
Bhojwani, P [1 ]
Mahapatra, R [1 ]
Kim, EJ [1 ]
Chen, T [1 ]
机构：
[1] Texas A&M Univ, Dept Comp Sci, College Stn, TX 77843 USA
来源：
18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS | 2005年
关键词：
D O I：
10.1109/ICVD.2005.12
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system components and routing of system communication affect system performance and power consumption. This research provides a heuristic to determine the neighborhood configuration for each component. By controlling the communication bandwidth allocation, simulation results with synthetic and real workloads indicate that our heuristic is able to control the peak power consumption, but at cost of throughput degradation.
引用
收藏
页码：124 / 129
页数：6
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