Modeling and Simulation of Negative Capacitance Gate on Ge FETs

In this work, a polysilicon-ferroelectric gate capacitor is proposed to be stacked on the Ge-MOSFET to simultaneously maintain the stability and the potential amplification in the sub-threshold region of a Negative Capacitance Field Effect Transistor. Hence, the non-hysteresis ID-VG characteristics with sub-60mV/dec subthreshold slope can be designed. A simple capacitance model including the effects of gate-to-source/drain overlap, interface trap states at oxide/Ge, and polysilicon/FE/metal is presented to analyze the subthreshold behavior. The optimized SS is further improved when the direct S/D overlap with floating metal of Ge-MOSFET increases. The polysilicon doping concentration causes the trade-off between subthreshold swing and hysteresis-free maximum voltage. The impact of the interface traps at the FE/poly interface on the device performance and the optimization approach are also discussed.