Scaling of InGaAs MOSFETs into deep-submicron

被引:1
|
作者
Wu, Yanqing [1 ]
Ye, Peide D. [1 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, Birck Nanotechnol Ctr, W Lafayette, IN 47907 USA
关键词
HIGH-PERFORMANCE; GATE; CHANNEL; TRANSISTOR; MOBILITY; HFALO;
D O I
10.1149/1.3367950
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
We have demonstrated high-performance deep-submicron inversion-mode InGaAs MOSFETs with gate lengths down to 150 nm with record G(m) exceeding 1.1 mS/mu m. Oxide thickness scaling is performed to improve the on-state/off-state performance and G(m) is further improved to 1.3 mS/mu m. HBr pre-cleaning, retro-grade structure and halo-implantation processes are first time introduced into III-V MOSFETs to steadily improve high-k/InGaAs interface quality and on-state/off-state performance of the devices. We have also demonstrated the first well-behaved inversion-mode InGaAs FinFET with ALD Al2O3 as gate dielectric using novel damage-free etching techniques. Detailed analysis of SS, DIBL and VT roll-off are carried out on FinFETs with L-ch down to 100 nm and W-Fin down to 40 nm. The short-channel effect (SCE) of planar InGaAs MOSFETs is greatly improved by the 3D structure design. The result confirms that the newly developed dry/wet etching process produces damage-free InGaAs sidewalls and the high-k/3D InGaAs interface is comparable to the 2D case.
引用
收藏
页码:185 / 201
页数:17
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