REALIZATION OF DEEP-SUBMICRON MOSFETS BY LATERAL ETCHING

被引：5
|
作者：
BURMESTER, R
WINNERL, J
NEPPL, F
机构：
[1] Siemens AG Corporate Research and Development Otto-Hahn-Ring 6
来源：
MICROELECTRONIC ENGINEERING | 1991年 / 13卷 / 1-4期
关键词：
D O I：
10.1016/0167-9317(91)90136-2
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A lateral etching technique is presented that allows the reproducible realization of 0.2-mu-m lines with a standard 1.0-mu-m g-line stepper lithography. The lateral etching was applied to the submicron device development. MOSFETs with quarter-micron gate lengths were successfully fabricated with standard lithography. A further application is to boost performance of an existing technology by reducing the gate length without increasing the lithography requirements.
引用
收藏
页码：473 / 476
页数：4
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