Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits

被引:0
|
作者
Nunez, Juan [1 ]
Avedillo, Maria J. [1 ]
Quintana, Jose M. [1 ]
机构
[1] Univ Seville, IMSE, Inst Microelect Sevilla, CNM,CSIC, Seville, Spain
关键词
TUNNELING CHAOS CIRCUIT;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an "all MOS" version of one previously reported which uses Resonant Tunneling Diodes (RTDs). The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.
引用
收藏
页码:480 / 483
页数:4
相关论文
共 50 条
  • [1] Novel voltage-controlled oscillator design by MOS-NDR devices and circuits
    Liang, DS
    Gan, KJ
    Hsiao, CC
    Tsai, CS
    Chen, YH
    Wang, SY
    Kuo, SH
    Chiang, FC
    Su, LX
    [J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 372 - 375
  • [2] Single Phase MOS-NDR MOBILE Networks
    Nunez, Juan
    Avedillo, Maria J.
    Quintana, Jose M.
    [J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 153 - 156
  • [3] Logic circuit design based on MOS-NDR devices and circuits fabricated by CMOS process
    Gan, KJ
    Liang, DS
    Hsiao, CC
    Wang, SY
    Chiang, FC
    Tsai, CS
    Chen, YH
    Kuo, SH
    Chen, CP
    [J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 392 - 395
  • [4] Efficient realisation of MOS-NDR threshold logic gates
    Nunez, J.
    Avedillo, M. J.
    Quintana, J. M.
    [J]. ELECTRONICS LETTERS, 2009, 45 (23) : 1158 - 1159
  • [5] Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits
    Liang, DS
    Gan, KJ
    Su, LX
    Chen, CP
    Hsiao, CC
    Tsai, CS
    Chen, YH
    Wang, SY
    Kuo, SH
    Chiang, FC
    [J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 78 - 81
  • [6] Design of multi-threshold threshold gate using MOS-NDR circuits suitable for CMOS process
    Gan, Kwang-Jow
    Huang, Chien-Hsiung
    Yeh, Wen-Kuan
    Guo, Chun-Yi
    Lu, Jeng-Jong
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2018, 96 (03) : 409 - 416
  • [7] Design of multi-threshold threshold gate using MOS-NDR circuits suitable for CMOS process
    Kwang-Jow Gan
    Chien-Hsiung Huang
    Wen-Kuan Yeh
    Chun-Yi Guo
    Jeng-Jong Lu
    [J]. Analog Integrated Circuits and Signal Processing, 2018, 96 : 409 - 416
  • [8] Four-valued memory circuit using three-peak MOS-NDR devices and circuits
    Gan, K. -J.
    Chen, Y. -H.
    Tsai, C. -S.
    Su, L. -X.
    [J]. ELECTRONICS LETTERS, 2006, 42 (09) : 514 - 515
  • [9] Compact and Power Efficient MOS-NDR Muller C-Elements
    Nunez, Juan
    Avedillo, Maria J.
    Quintana, Jose M.
    [J]. TECHNOLOGICAL INNOVATION FOR VALUE CREATION, 2012, 372 : 437 - 442
  • [10] A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology
    Wang Wei
    Huang Beiju
    Dong Zan
    Guo Weilian
    Chen Hongda
    [J]. JOURNAL OF SEMICONDUCTORS, 2010, 31 (05)