共 50 条
- [41] A statistical model for path delay faults in VLSI circuits PROCEEDINGS OF THE IEEE SOUTHEASTCON '96: BRINGING TOGETHER EDUCATION, SCIENCE AND TECHNOLOGY, 1996, : 388 - 392
- [42] A TEST-GENERATION SYSTEM FOR PATH DELAY FAULTS PROCEEDINGS - IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS & PROCESSORS, 1989, : 40 - 43
- [43] ON DESIGNING ROBUST TESTABLE PLA FOR PATH DELAY FAULTS TWENTY-THIRD ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2: CONFERENCE RECORD, 1989, : 999 - 1001
- [45] PARALLEL PATTERN FAULT SIMULATION OF PATH DELAY FAULTS 26TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, 1989, : 357 - 363
- [48] Multiple Faults Diagnosability of Hybrid Systems MED: 2009 17TH MEDITERRANEAN CONFERENCE ON CONTROL & AUTOMATION, VOLS 1-3, 2009, : 365 - 370
- [49] Improving diagnostic resolution of delay faults using path delay fault model 21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2003, : 345 - 350
- [50] Critical Path Tracing based Simulation of Transition Delay Faults 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, : 108 - 113