共 50 条
- [1] A 36-Gb/s Adaptive Baud-Rate CDR With CTLE and 1-Tap DFE in 28-nm CMOS [J]. IEEE SOLID-STATE CIRCUITS LETTERS, 2019, 2 (11): : 252 - 255
- [2] A 22.5-to-32Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in 28nm CMOS [J]. 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 120 - 120
- [5] A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 μm BiCMOS technology [J]. IEICE ELECTRONICS EXPRESS, 2020, 17 (05):
- [6] A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS [J]. 2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 28 - +
- [7] A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuit with One-tap DFE [J]. 2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,
- [10] A 1-tap 10.3125Gb/s Programmable Voltage Mode Line Driver in 28nm CMOS Technology [J]. 2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2016, : 174 - 178