A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range

被引：1
|
作者：
Chou, Po-Yuan [1 ,2 ]
Chen, Wei-Ming [1 ,2 ]
Liu, Shen-Iuan [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2024年 / 32卷 / 03期
关键词：
Asymmetrical phase detector; baud-rate; clock and data recovery (CDR); digital place-and-route tools; frequency capture range (FCR); RATE DIGITAL CDR; TRANSMITTER; CALIBRATION; RECEIVER;
D O I：
10.1109/TVLSI.2024.3353197
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm(2) . For a 16 Gb/s PRBS of 2(7)-1, the power of the CDR circuit is 38.4 mW and its calculated energy efficiency is 2.4 pJ/b. The measured FCR is 40.6%.
引用
收藏
页码：480 / 484
页数：5
相关论文
共 23 条
  • [1] A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection
    Peng, Hsi-Kai
    Liu, Shen-Iuan
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 32 (04) : 787 - 791
  • [2] A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuit with One-tap DFE
    Peng, Hsi-Kai
    Liu, Shen-Iuan
    2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,
  • [3] A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD
    Chen, Wei-Ming
    Yao, Yun-Sheng
    Liu, Shen-Iuan
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68 (11) : 4566 - 4575
  • [4] A 14.7-20-Gb/s Reference-Less Baud-rate CDR Circuit with One-Tap DFE and Time-Interpolation
    Chou, Po-Yuan
    Liu, Shen-Iuan
    2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,
  • [5] A 48-Gb/s Baud-Rate PAM-4 Receiver With One-Tap Speculative DFE and Reused Comparators
    Huang, Yuan-Pang
    Liu, Shen-Iuan
    2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,
  • [6] A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth
    Francese, Pier Andrea
    Toifl, Thomas
    Buchmann, Peter
    Braendli, Matthias
    Menolfi, Christian
    Kossel, Marcel
    Morf, Thomas
    Kull, Lukas
    Andersen, Toke Meyer
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (11) : 2490 - 2502
  • [7] A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE
    Lin, Jhe-En
    Liu, Shen-Iuan
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2025, 33 (01) : 168 - 178
  • [8] A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS
    Yoo, Danny
    Bagherbeik, Mohammad
    Rahman, Wahid
    Sheikholeslami, Ali
    Tamura, Hirotaka
    Shibasaki, Takayuki
    2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2019, 62 : 126 - +
  • [9] A 36-Gb/s Adaptive Baud-Rate CDR With CTLE and 1-Tap DFE in 28-nm CMOS
    Yoo, Danny
    Bagherbeik, Mohammad
    Rahman, Wahid
    Sheikholeslami, Ali
    Tamura, Hirotaka
    Shibasaki, Takayuki
    IEEE SOLID-STATE CIRCUITS LETTERS, 2019, 2 (11): : 252 - 255
  • [10] A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE
    Chen, Wei-Ming
    Yao, Yun-Sheng
    Liu, Shen-Iuan
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (03) : 894 - 898
123