A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range

被引：1
|
作者：
Chou, Po-Yuan [1 ,2 ]
Chen, Wei-Ming [1 ,2 ]
Liu, Shen-Iuan [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2024年 / 32卷 / 03期
关键词：
Asymmetrical phase detector; baud-rate; clock and data recovery (CDR); digital place-and-route tools; frequency capture range (FCR); RATE DIGITAL CDR; TRANSMITTER; CALIBRATION; RECEIVER;
D O I：
10.1109/TVLSI.2024.3353197
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm(2) . For a 16 Gb/s PRBS of 2(7)-1, the power of the CDR circuit is 38.4 mW and its calculated energy efficiency is 2.4 pJ/b. The measured FCR is 40.6%.
引用
收藏
页码：480 / 484
页数：5
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