20μm deep trench isolation process characterisation for linear bipolar ICs

The use of junction isolation in linear bipolar ICs substantially consumes silicon area. The replacement of junction isolation with trench isolation has the potential to significantly reduce device area while maintaining high voltage operation. Deep trench isolation has been implemented on a conventional non-complementary 40V (NPN BVceo) linear IC process. A fully functional low power operational amplifier has been fabricated as a technology driver. Device characterisation shows that transistor leakage currents (I-ceo) and leakage between trench tubs can be made comparable with junction isolated devices. The NPN buried layer (BL) can successfully be butted against the trench sidewall without device degradation, although this is currently not possible with the NPN base. Am NPN device shrink of 3x has been achieved and further development is underway to increase this towards the 4x level, where the base diffusion front touches the trench sidewall.