Investigation of Latch-up Immunity in 0.18-μm BCD Process with Deep Trench Isolation

被引：0

作者：

Ho, Wen-Yung ^{[1
]}

Ker, Ming-Dou ^{[1
]}

Wang, Chun-Chi ^{[2
]}

Chiang, Tsung-Yin ^{[2
]}

Wei, I-Ju ^{[2
]}

机构：

[1] Natl Yang Ming Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

[2] Elan Microelect Corp, Hsinchu, Taiwan

来源：

2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA | 2024年

关键词：

Deep Trench Isolation (DTI); LDMOS; Latch-up;

D O I：

10.1109/VLSITSA60681.2024.10546435

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Deep Trench Isolation (DTI) is a specialized isolation technique employed in the BCD process to mitigate latch-up issues. Unlike junction isolation, which was typically implemented by guard rings, the DTI offers a significant reduction in layout area due to its physical isolation capabilities. This study delves into the impact of DTI on latch-up immunity between 100-V LDMOS in the I/O circuits and the additional guard ring between the 100-V I/O circuits and 5-V internal circuits. The results of this study will be benefit to the high-voltage IC products, that drawn with reduced layout spacing but having high latch-up immunity.

引用

页数：2

共 31 条

[1] Investigation on Latch-Up Path between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process
Chen, Chun-Cheng
Ker, Ming-Dou
2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2019,
[2] Schottky-Embedded Isolation Ring to Improve Latch-Up Immunity Between HV and LV Circuits in a 0.18 μm BCD Technology
Jiang, Zi-Hong
Ker, Ming-Dou
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2022, 10 : 516 - 524
[3] The impact of trench isolation on latch-up immunity in bulk nonepitaxial CMOS
Bhattacharya, S., 1600, (12):
[4] THE IMPACT OF TRENCH ISOLATION ON LATCH-UP IMMUNITY IN BULK NONEPITAXIAL CMOS
BHATTACHARYA, S
BANERJEE, S
LEE, J
TASCH, A
CHATTERJEE, A
IEEE ELECTRON DEVICE LETTERS, 1991, 12 (02) : 77 - 79
[5] OPTIMIZATION OF DEEP TRENCH ISOLATION ON 0.18μm SOI BCD TECHNOLOGY FOR AUTOMOTIVE APPLICATION
Salleh, Siti Aisah Binti Mohd
Ching, Sim Poh
CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC, 2024,
[6] NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-μm BCD Process
Chen, Chao-Yang
Lee, Jian-Hsing
Nidhi, Karuna
Bin, Tzer-Yaa
Lin, Geeng-Lih
Ker, Ming-Dou
2021 43RD ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2021,
[7] Investigation on the Turn-on Time of RC-Triggered Power Clamps Based on 0.18-μm BCD Process
Zheng, Yifei
Jin, Xiangliang
Wu, Jianfei
Wang, Yang
Zhang, Ang
Zhang, Hongli
2019 12TH INTERNATIONAL WORKSHOP ON THE ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS (EMC COMPO 2019), 2019, : 192 - 194
[8] Investigation of ESD devices in 0.18-μm SiGeBiCMOS process
Chen, SS
Chen, TY
Tang, TH
Hsu, TL
Tseng, HC
Chen, JK
Chou, CH
41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2003, : 357 - 360
[9] Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18-μm CMOS Technology
Chen, Chun-Cheng
Ker, Ming-Dou
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2019, 19 (02) : 445 - 451
[10] n-p-n Array Yield Improvement in a 0.18-μm Deep Trench SiGe BiCMOS Process
Gan, Dong
Hu, Chun
Parker, George E.
Pao, Henry H.
Jolly, Gurvinder
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (03) : 590 - 595

← 1 2 3 4 →