Investigation of Latch-up Immunity in 0.18-μm BCD Process with Deep Trench Isolation

被引：0

作者：

Ho, Wen-Yung ^{[1
]}

Ker, Ming-Dou ^{[1
]}

Wang, Chun-Chi ^{[2
]}

Chiang, Tsung-Yin ^{[2
]}

Wei, I-Ju ^{[2
]}

机构：

[1] Natl Yang Ming Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

[2] Elan Microelect Corp, Hsinchu, Taiwan

来源：

2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA | 2024年

关键词：

Deep Trench Isolation (DTI); LDMOS; Latch-up;

D O I：

10.1109/VLSITSA60681.2024.10546435

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Deep Trench Isolation (DTI) is a specialized isolation technique employed in the BCD process to mitigate latch-up issues. Unlike junction isolation, which was typically implemented by guard rings, the DTI offers a significant reduction in layout area due to its physical isolation capabilities. This study delves into the impact of DTI on latch-up immunity between 100-V LDMOS in the I/O circuits and the additional guard ring between the 100-V I/O circuits and 5-V internal circuits. The results of this study will be benefit to the high-voltage IC products, that drawn with reduced layout spacing but having high latch-up immunity.

引用

页数：2

共 31 条

[21] Total Ionizing Dose and Single Event Latch-up Characterization of a 16-bit A-to-D Converter Fabricated in 0.18μm Triple-Well CMOS Process
Zanchi, Alfio
Hisano, Shinichi
Hafer, Craig
Kerwin, David B.
2012 IEEE RADIATION EFFECTS DATA WORKSHOP (REDW), 2012,
[22] 20μm deep trench isolation process characterisation for linear bipolar ICs
Dyer, T
Doohan, I
Fallon, M
McAlpine, D
Aitkenhead, A
McGinty, J
Taylor, M
Gravelle, P
Schouten, A
Bryce, M
PROCESS AND EQUIPMENT CONTROL IN MICROELECTRONIC MANUFACTURING II, 2001, 4405 : 117 - 122
[23] A manufacturable shallow trench isolation process for 0.18μm and beyond-optimization, stress reduction and electrical performance
Nouri, F
Laparra, O
Sur, H
Tai, GC
Pramanik, D
Manley, M
ASMC 98 PROCEEDINGS - 1998 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: THEME - SEMICONDUCTOR MANUFACTURING: MEETING THE CHALLENGES OF THE GLOBAL MARKETPLACE, 1998, : 413 - 418
[24] Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process
Lin, Chun-Yu
Chiu, Yan-Lian
MICROELECTRONICS RELIABILITY, 2015, 55 (11) : 2229 - 2235
[25] Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)
Hirano, Y
Maeda, S
Matsumoto, T
Nii, K
Iwamatsu, T
Yamaguchi, Y
Ipposhi, T
Kawashima, H
Maegawa, S
Inuishi, M
Nishimura, T
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (12) : 2816 - 2822
[26] A miniature, folded-switching, up-conversion mixer for UWB applications using 0.18-μm CMOS process
Huang, Pin-Cheng
Chang, Fong-Cheng
Chao, Shih-Fong
Wang, Huei
2007 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2007, : 501 - +
[27] A High-Isolation High-Linearity 24-GHz CMOS T/R Switch in the 0.18-μm CMOS Process
Ou, C. -Y
Hsu, C. -Y.
Lin, H. -R.
Chuang, H. -R
2009 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC 2009), 2009, : 250 - 253
[28] A 0.18-μm CMOS CMFB downconversion micromixer with deep N-well technology for LO-RF and LO-IF isolation improvements
Meng, CC
Hsu, SK
Wu, TH
Huang, GW
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2005, 45 (02) : 168 - 170
[29] Influences of Substrate Pickup Integrated with the Source-end Engineering on ESD/Latch-up Reliabilities in a 0.35-μm 3.3-V Process
Chen, Shen-Li
Lee, Min-Hua
Wu, Tzung-Shian
2016 INTERNATIONAL SYMPOSIUM ON COMPUTER, CONSUMER AND CONTROL (IS3C), 2016, : 632 - 635
[30] A 0.24-μm2 cell process with 0.18-μm width isolation and 3-D interpoly dielectric films for 1-Gb flash memories
Kobayashi, T
Matsuzaki, N
Sato, A
Katayama, A
Kurata, H
Miura, A
Mine, T
Goto, Y
Morimoto, T
Kume, H
Kure, T
Kimura, K
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 275 - 278

← 1 2 3 4 →