A manufacturable shallow trench isolation process for 0.18μm and beyond-optimization, stress reduction and electrical performance

被引：4

作者：

Nouri, F ^{[1
]}

Laparra, O ^{[1
]}

Sur, H ^{[1
]}

Tai, GC ^{[1
]}

Pramanik, D ^{[1
]}

Manley, M ^{[1
]}

机构：

[1] VLSI Technol Inc, Technol Dev, San Jose, CA 95131 USA

来源：

ASMC 98 PROCEEDINGS - 1998 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: THEME - SEMICONDUCTOR MANUFACTURING: MEETING THE CHALLENGES OF THE GLOBAL MARKETPLACE | 1998年

关键词：

D O I：

10.1109/ASMC.1998.731638

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An integrated shallow trench isolation process utilizing HDP (High Density Plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 mu m technologies.

引用

页码：413 / 418

页数：6

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