Electrical Analysis of Mechanical Stress Induced by Shallow Trench Isolation

被引：0

作者：

Jiang, Yanfeng ^{[1
]}

Ju, Jiaxin ^{[1
]}

机构：

[1] N China Univ Technol, Coll Informat Engn, Ctr Microelect, Beijing 100144, Peoples R China

来源：

2009 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2009) | 2009年

关键词：

SHORT-CHANNEL MOSFETS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In many modern technologies, shallow trench isolation (STI) exhibits a potential application, especially for power devices or SOI ones. During its application, technologies have found the mechanical stress which originated from STI technology. This paper describes the usage of STI on power devices, which fulfills 700V technology on 100V BCD technology. Main results are the mobility variations with stress, the strong effect of Rsd on transistors. Then using the same approach on short devices with different distances gate edge to STI, we show how to evaluate stress distribution induced by STI as well as its mean value under the gate of the devices. These results help to understand, minimize or optimize stress effects.

引用

下载

页码：1155 / 1158

页数：4

共 50 条

[1] Electrical analysis of mechanical stress induced by shallow trench isolation
Gallon, C
Reimbold, G
Ghibaudo, G
Bianchi, RA
Gwoziecki, R
Raynaud, C
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 359 - 362
[2] NMOS Drive Current Enhancement by Reducing Mechanical Stress Induced by Shallow Trench Isolation
Innocenti, J.
Rivero, C.
Julien, F.
Portal, J. M.
Hubert, Q.
Bouton, G.
Fornara, P.
Lopez, L.
Masson, P.
Niel, S.
Regnier, A.
PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 395 - 398
[3] Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance
Bianchi, RA
Bouche, G
Roux-dit-Buisson, O
INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 117 - 120
[4] Effect of shallow trench isolation induced stress on CMOS transistor mismatch
Tan, PBY
Kordesch, AV
Sidek, O
2004 IEEE International Conference on Semiconductor Electronics, Proceedings, 2004, : 189 - 192
[5] Mechanical stress characterization of shallow trench isolation by Kelvin probe force microscopy
Rueda, H
Slinkman, J
Chidambarrao, D
Moszkowicz, L
Kaszuba, P
Law, M
SI FRONT-END PROCESSING-PHYSICS AND TECHNOLOGY OF DOPANT-DEFECT INTERACTIONS, 1999, 568 : 245 - 250
[6] Stress analysis of shallow trench isolation for 256MDRAM and beyond
Kuroi, T
Uchida, T
Horita, K
Sakai, M
Itoh, Y
Inoue, Y
Nishimura, T
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, : 141 - 144
[7] Channel width dependence of mechanical stress effects induced by shallow trench isolation on device performance of nanoscale nMOSFETs
Lee, Seonhaeng
Kim, Dongwoo
Kim, Cheolgyu
Lee, Chiho
Park, Jeongsoo
Kang, Bongkoo
MICROELECTRONICS RELIABILITY, 2012, 52 (9-10) : 1949 - 1952
[8] Photoresist chemical mechanical polishing for shallow trench isolation
Itoh, A
Imai, M
Arimoto, K
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1998, 37 (4A): : 1697 - 1700
[9] Photoresist chemical mechanical polishing for shallow trench isolation
Itoh, Akio
Imai, Masahiko
Arimoto, Yoshihiro
Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes & Review Papers, 1998, 37 (4 A): : 1697 - 1700
[10] Shallow Trench Isolation Chemical Mechanical Planarization: A Review
Srinivasan, Ramanathan
Dandu, Pradeep V. R.
Babu, S. V.
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2015, 4 (11) : P5029 - P5039

← 1 2 3 4 5 →