Investigation of Latch-up Immunity in 0.18-μm BCD Process with Deep Trench Isolation

被引：0

作者：

Ho, Wen-Yung ^{[1
]}

Ker, Ming-Dou ^{[1
]}

Wang, Chun-Chi ^{[2
]}

Chiang, Tsung-Yin ^{[2
]}

Wei, I-Ju ^{[2
]}

机构：

[1] Natl Yang Ming Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

[2] Elan Microelect Corp, Hsinchu, Taiwan

来源：

2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA | 2024年

关键词：

Deep Trench Isolation (DTI); LDMOS; Latch-up;

D O I：

10.1109/VLSITSA60681.2024.10546435

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Deep Trench Isolation (DTI) is a specialized isolation technique employed in the BCD process to mitigate latch-up issues. Unlike junction isolation, which was typically implemented by guard rings, the DTI offers a significant reduction in layout area due to its physical isolation capabilities. This study delves into the impact of DTI on latch-up immunity between 100-V LDMOS in the I/O circuits and the additional guard ring between the 100-V I/O circuits and 5-V internal circuits. The results of this study will be benefit to the high-voltage IC products, that drawn with reduced layout spacing but having high latch-up immunity.

引用

页数：2