A 12-bit 100 MS/s pipelined ADC without using front-end SHA

被引：2

作者：

Imanpoor, H. ^{[1
]}

Mehranpouy, M. ^{[1
]}

Torkzadeh, P. ^{[1
]}

Jannesari, A. ^{[2
]}

机构：

[1] Islamic Azad Univ, Dept Elect & Comp Engn, Sci & Res Branch, Tehran, Iran

[2] Tarbiat Modares Univ, Dept Elect & Comp Engn, Tehran, Iran

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2018年 / 86卷

关键词：

Pipeline Analog-to-Digital Converter (ADC); SHA-Free; Low power consumption; Comparator; Operational amplifier; Digital-to-Analog Converter (DAC); CMOS; CONVERTER; DESIGN;

D O I：

10.1016/j.aeue.2018.01.027

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a model and a novel architecture of a low-power pipelined analog-to-digital converter (ADC) without using front-end Sample and Hold Amplifier (SHA) stage. The modeling of all ADC building blocks along with their non-ideal effects have been implemented in MATLAB SIMULINK environment and the main transistor level circuits have been implemented in H-SPICE environment using 180-nm TSMC CMOS technology. The maximum DNL and INL amounts are equal to +/- 0.9 LSB and 2.3 LSB, respectively. Applying a 33.1 MHz with 1.4 Vp-p (-6dBFS) input signal, achieved SNOB is 61 dB resulting in 9.8 Bits ENOB with total power consumption of 42 mW.

引用

页码：142 / 153

页数：12

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