共 50 条
- [31] The Characterization of Errors in an FPGA-Based RISC-V Processor due to Single Event Transients MICROELECTRONICS JOURNAL, 2022, 123
- [32] FlushBlocker: Lightweight mitigating mechanism for CPU cache flush instruction based attacks 2021 IEEE EUROPEAN SYMPOSIUM ON SECURITY AND PRIVACY WORKSHOPS (EUROS&PW 2021), 2021, : 74 - 79
- [33] A Hardware based RISC-V Extension Instruction Implementation Mechanism and Implementation Example 2024 5TH INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING AND APPLICATION, ICCEA 2024, 2024, : 372 - 381
- [35] A Dynamic Approximation Processor Based on Out-of-Order RISC-V in 28-nm CMOS 2024 IEEE THE 20TH ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS 2024, 2024, : 509 - 513
- [40] A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications 18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021), 2021, : 375 - 376