A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise

被引：4

作者：

Murphy, David ^{[1
]}

Yang, Dihang ^{[1
]}

Darabi, Hooman ^{[2
]}

Behzad, Arya ^{[3
]}

机构：

[1] Broadcom Inc, Irvine, CA 92618 USA

[2] Broadcom Inc, Wireless Connect Grp, Irvine, CA 92618 USA

[3] Broadcom Inc, San Jose, CA 95131 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2023年 / 58卷 / 09期

关键词：

Clocks; Phase locked loops; Timing; Voltage-controlled oscillators; Quantization (signal); Phase frequency detectors; Prototypes; CMOS; inductor-capacitor (LC); Index Terms; oscillator; phase noise; phase-locked loop (PLL); voltage-controlled oscillator (VCO); OSCILLATOR; SYNTHESIZER;

D O I：

10.1109/JSSC.2023.3263075

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analog fractional -N phase-locked loop (PLL) is presented, which largely eliminates quantization noise by overclocking the delta-sigma modulator (DSM). The overclocking technique, enabled by a multipath phase detector and linear resistor-DAC (RDAC) recombination, does not require a high-reference frequency and does not require calibration. A low power 7-nm prototype operating at 4.884 GHz exhibits 154-fs rms jitter and a figure of merit (FOM) of 255.8 dB.

引用

页码：2513 / 2525

页数：13

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