A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise

被引：4

作者：

Murphy, David ^{[1
]}

Yang, Dihang ^{[1
]}

Darabi, Hooman ^{[2
]}

Behzad, Arya ^{[3
]}

机构：

[1] Broadcom Inc, Irvine, CA 92618 USA

[2] Broadcom Inc, Wireless Connect Grp, Irvine, CA 92618 USA

[3] Broadcom Inc, San Jose, CA 95131 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2023年 / 58卷 / 09期

关键词：

Clocks; Phase locked loops; Timing; Voltage-controlled oscillators; Quantization (signal); Phase frequency detectors; Prototypes; CMOS; inductor-capacitor (LC); Index Terms; oscillator; phase noise; phase-locked loop (PLL); voltage-controlled oscillator (VCO); OSCILLATOR; SYNTHESIZER;

D O I：

10.1109/JSSC.2023.3263075

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analog fractional -N phase-locked loop (PLL) is presented, which largely eliminates quantization noise by overclocking the delta-sigma modulator (DSM). The overclocking technique, enabled by a multipath phase detector and linear resistor-DAC (RDAC) recombination, does not require a high-reference frequency and does not require calibration. A low power 7-nm prototype operating at 4.884 GHz exhibits 154-fs rms jitter and a figure of merit (FOM) of 255.8 dB.

引用

页码：2513 / 2525

页数：13

共 50 条

[31] Evolution and maturity of fractional-N PLL synthesis
Goldberg, B.C.
Microwave Journal, 1996, 39 (09)
[32] A new fractional-N PLL frequency synthesizer
Sumi, Y
Obote, S
Fukui, Y
Tsuda, K
Syoubu, K
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 1997, 7 (05) : 395 - 405
[33] PLL fractional-N synthesizers to 14 GHz
Microwave Journal, 2009, 52 (09): : 172 - 176
[34] Phase-Blender-Based FIR Noise Filtering Techniques for ΔΣ Fractional-N PLL
Jee, Dong-Woo
Suh, Yunjae
Park, Hong-June
Sim, Jae-Yoon
2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
[35] An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators
Yu, Xueyi
Sun, Yuanfeng
Rhee, Woogeun
Wang, Zhihua
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (09) : 2426 - 2436
[36] A Quantization Noise Cancelling Fractional-N type ΔΣ Frequency Synthesizer using SAR-based DAC Gain Calibration
Kim, Seungjin
Lee, In-Young
Kim, Joo-Myoung
Lee, Sang-Gug
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
[37] Phase noise cancellation for a Σ-Δ fractional-N PLL employing a sample-and-hold element
Liu, Lechang
Li, Binhong
2005 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS, VOLS 1-5, 2005, : 3297 - 3300
[38] A Compact, Low-Phase Noise Fractional-N PLL for Global Navigation Receiver
Kharalkar, Ajinkya
Pancholi, Mukul
Kanchetla, Vijaya Kumar
Khade, Aniruddha
Khyalia, Santosh
Hameed, Syed
Zele, Rajesh
2021 19TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2021,
[39] Customized Zero Frequency Control for Hybrid FIR Noise Filtering in ΔΣ Fractional-N PLL
Qiao, Jian
Yu, Xueyi
Rhee, Woogeun
Wang, Zhihua
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2401 - +
[40] Behavioral modeling and simulation of jitter and phase noise in fractional-N PLL frequency synthesizer
Mao, XJ
Yang, HZ
Wang, H
BMAS 2004: IEEE INTERNATIONAL BEHAVIORAL MODELING AND SIMULATION CONFERENCE - PROCEEDINGS, 2004, : 25 - 30

← 1 2 3 4 5 →