Area, power efficient Vedic multiplier architecture using novel 4:2 compressor

A multiplier is a key component in arithmetic and logical units. So low power consuming, area efficient speedy multiplier architecture is need of today's Arithmetic and Logic Unit. In the ancient Indian Vedic mathematics, the Urdhvatiryagbhyam sutra gives a multiplication methodology. Vedic multiplier improves the performance parameters of the digital circuit logically as well as physically. The performance of the multiplier depends upon a reduction in partial product generation. This is achieved with the help of a 4:2 compressor. In this paper, a logically improved, area-optimized 4:2 compressor is proposed. The proposed design is implemented in standard CMOS 45 nm technology and analyzed the results post layout design. For performance analysis, the novel proposed 4:2 compressor is used in a Vedic multiplier. After simulation, we get results which shows that the proposed compressor has 62.95% of power reduction and 53.31% delay reduction compared to the conventional compressor. The compressor shows a 44.34-10.57% reduction in ADP and 149.84-12.59% reduction in PDP against present variants. The proposed 4 Bit Vedic multiplier shows a 9.633% power reduction compared to the Vedic multiplier with a conventional compressor. The 4 Bit Vedic multiplier shows a 44.877-7.14% reduction in Area-Delay product and 27.99-0.22% reduction in Power-Delay product against present variants.