Low Power Vedic Multiplier Using Energy Recovery Logic

Multiplier is one of the primary hardware blocks in modern day digital signal processing (DSP) and communication systems. It is extensively used in DSP and image processing applications such as, Fast Fourier Transform (FFT), convolution, correlation, filtering and in ALU of microprocessors. Therefore, high speed, low area and power efficient multiplier design remain the critical factors for the overall system. This paper presents high performance and energy efficient implementation of the binary multiplier. The design is based on ancient Indian Vedic multiplication process and the low power energy recovery (aka adiabatic logic). The generation of partial sums and products in a single step in the Vedic approach and the energy recovery capability of the adiabatic logic together realize high speed and low power operation of the design. A 16X16 Vedic multiplier and conventional array multiplier based on the Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) is proposed in the paper. Simulation results validate this design incurring 87.21 percent lesser power than the standard CMOS equivalent design.