Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits

This paper deals with an innovative structure of silicon-on-insulator junctionless transistor (SOIJLT) by incorporating a buried metal layer of proper work-function which creates the Schottky junction between device layer and the buried metal layer. The buried metal layer results in perfect volume inversion in OFF-state due to which in comparison to SOIJLT, the off-state current (I-OFF) of the proposed buried metal SOIJLT (BMSOIJLT) is significantly reduced. In addition, the short-channel effects such as subthreshold swing (SS) and the drain-induced barrier lowering (DIBL) in the proposed BMSOIJLT are reduced by 40% and 30% respectively over the SOIJLT device. The CMOS digital logic circuits such as inverter, NAND gate and the NOR gate have also been implemented using the mixed-mode device/circuit simulations. Despite due to lower ON-state drive current (I-ON) and the parasitic capacitances in the proposed BMSOIJLT, the propagation delay in SOIJLT and the proposed BMSOIJLT based logic gates is comparable. Moreover, due to significant reduction in I-OFF the static power dissipation in the proposed BMSOIJLT based logic gates is significantly low.