共 50 条
- [43] A Monolithic 56 Gb/s CMOS Integrated Nanophotonic PAM-4 Transmitter [J]. 2015 IEEE OPTICAL INTERCONNECTS CONFERENCE, 2015, : 16 - 17
- [45] A 50Gb/s PAM-4 Retimer-CDR plus VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die [J]. 2019 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXHIBITION (OFC), 2019,
- [46] 2-to-1 selector IC in 90-nm CMOS technology operating up to 50 Gb/s [J]. 2004 IEEE CSIC SYMPOSIUM, TECHNICAL DIGEST 2004: 26TH ANNIVERSARY: COMPOUNDING YOUR CHIPS IN MONTEREY, 2004, : 243 - 246
- [47] A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS [J]. 2019 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC), 2019, : 299 - 302
- [49] A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS [J]. IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023, 2023, : 373 - 376
- [50] A 40-Gb/s Transmitter with 4:1 MUX and Subharmonically Injection-Locked CMU in 90-nm CMOS Technology [J]. 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 48 - 49