Design and optimization of vertical nanowire tunnel FET with electrostatic doping

被引:8
|
作者
Bhardwaj, Anjana [1 ]
Kumar, Pradeep [1 ]
Raj, Balwinder [2 ]
Kumar, Naveen [3 ]
Anand, Sunny [4 ]
机构
[1] Amity Univ Uttar Pradesh, Noida, India
[2] NIT, Jalandhar, India
[3] Univ Glasgow, Glasgow, Scotland
[4] HCL, Noida, India
来源
ENGINEERING RESEARCH EXPRESS | 2023年 / 5卷 / 04期
关键词
electrostatic; dopingless; intrinsic; SCE; RDF; abrupt doping; vertical nanowire TFET; FIELD-EFFECT TRANSISTOR; TFET;
D O I
10.1088/2631-8695/acff3a
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
While dealing with the nanoscale regime, most devices make sacrifices in terms of performance. So to meet the performance requirements, Electrostatic doped Vertical Nanowire Tunnel Field Effect Transistor (E-VNWTFET) is proposed and analysed in this work. The dimensions of Electrostatic VNWTFET structure are scaled down and then the analog performance parameters transconductance g(m), g(m2) (2nd order), g(m3) (3rd order) and linearity parameters 2nd order Voltage Interception Point VIP2, 3rd order Voltage Interception Point VIP3, 3rd order Input Interception Point IIP3 and 3rd order Intermodulation Distortion IMD3 are analysed. It is observed that electrostatic technique of doping is better than charge plasma (CP) technique; because in CP technique costly metals are required for doping. The analog performance parameters of E-VNWTFET are investigated and using device simulation the demonstrated characteristics are compared with CP-VNWTFET. After simulation, the device exhibits ON current I-ON of 3.5 mu A mu m(-1) and OFF current I-OFF of 6.6 x 10(-18 )A mu m(-1); which offers a significant I-ON/I-OFF of 10(11). The reported subthreshold swing and Drain-induced barrier lowering DIBL are approx. 9.7 mV/Decade and 37.8 mV/V respectively.
引用
收藏
页数:12
相关论文
共 50 条
  • [1] Design and Performance Analysis of a GAA Electrostatic Doped Negative Capacitance Vertical Nanowire Tunnel FET
    Anjana Bhardwaj
    Pradeep Kumar
    Balwinder Raj
    Sunny Anand
    Journal of Electronic Materials, 2023, 52 : 3103 - 3111
  • [2] Design and Performance Analysis of a GAA Electrostatic Doped Negative Capacitance Vertical Nanowire Tunnel FET
    Bhardwaj, Anjana
    Kumar, Pradeep
    Raj, Balwinder
    Anand, Sunny
    JOURNAL OF ELECTRONIC MATERIALS, 2023, 52 (05) : 3103 - 3111
  • [3] Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET
    Jang, Won Douk
    Yoon, Young Jun
    Cho, Min Su
    Jung, Jun Hyeok
    Lee, Sang Ho
    Jang, Jaewon
    Bae, Jin-Hyuk
    Kang, In Man
    MICROMACHINES, 2019, 10 (11)
  • [4] Design and Analysis of Charge Plasma-Based Vertical-Nanowire Tunnel FET for Biosensor
    Kumar, Parveen
    Raj, Balwinder
    NANO, 2023, 18 (01)
  • [5] Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers
    Ko, Eunah
    Lee, Hyunjae
    Park, Jung-Dong
    Shin, Changhwan
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (12) : 5030 - 5035
  • [6] Vertical Tunnel FET Technology: Optimization and Reliability Perspective
    Wangkheirakpam, Vandana Devi
    Bhowmick, Brinda
    Pukhrambam, Puspa Devi
    2021 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PERFORMANCE EVALUATION (COMPE-2021), 2021, : 820 - 825
  • [7] Design Considerations and Optimization of Electrostatic Doped Ferroelectric Nanotube Tunnel FET: Analog and Noise Analysis
    Ashok Kumar Gupta
    Ashish Raman
    Naveen Kumar
    Silicon, 2022, 14 : 10357 - 10373
  • [8] Design Considerations and Optimization of Electrostatic Doped Ferroelectric Nanotube Tunnel FET: Analog and Noise Analysis
    Gupta, Ashok Kumar
    Raman, Ashish
    Kumar, Naveen
    SILICON, 2022, 14 (16) : 10357 - 10373
  • [9] Electrostatic Doping-Based All GNR Tunnel FET: An Energy-Efficient Design for Power Electronics
    Zhang, Weixiang
    Ragab, Tarek
    Basaran, Cemal
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (04) : 1971 - 1978
  • [10] Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
    Hu, Vita Pi-Ho
    Lin, Hung-Han
    Lin, Yen-Kai
    Hu, Chenming
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (06) : 2593 - 2599