An Innovative Program Scheme for Reducing Z-Interference in Charge-Trap-Based 3-D NAND Flash Memory

In this brief, we propose an innovative program scheme to mitigatez-direction interference(Z-interference) in charge-trap-based 3-DNANDflash memory. Our approach adjusts the position of trapped electronsin charge trap nitride (CTN) layer during the program oper-ation by varying the pass voltage (V-pass) on both side wordlines (WLs) of the selected WL. Specifically, cells with a high threshold voltage (V-th) place electrons in the program direction, whereas cells with a low V-th place electrons inthe opposite direction. Depending on the program-verify(PV) level pattern of the aggressor (Agr)-victim cell (Vic),the effective gate pitch can be modified, even though the physical gate pitch is fixed. We validate our proposed scheme using technology computer-aided design (TCAD)simulations and experimental measurements.