System-level reliability assessment of optical network on chip

被引:5
|
作者
Baharloo, Mohammad [1 ]
Abdollahi, Meisam [1 ]
Baniasadi, Amirali [1 ]
机构
[1] Univ Victoria, Elect & Comp Engn Dept, Victoria, BC, Canada
关键词
Silicon photonics; Optical Network on Chip; System-level reliability; Markov chain; Reliability Block Diagram; ON-CHIP; COMMUNICATION; SWITCH;
D O I
10.1016/j.micpro.2023.104843
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Optical Network on Chip (ONoC) is now considered a promising alternative to traditional electrical intercon-nects. Meanwhile, several challenges such as temperature and process variations, aging, crosstalk noise, and insertion loss endanger the data transmission reliability of ONoCs. Many investigations have been made to evaluate the effect of these phenomena on ONoC's reliability. However, system-level reliability assessment of ONoCs based on the failure rate of its essential elements has not been considered by the researchers yet. In this paper, we offer a reliability framework to calculate the reliability of micro-ring resonator, optical path, optical router, and optical topology architecture. Moreover, we developed a system-level simulator called Reliability Assessment of Photonic Network-on-Chips (RAP-NoC) to evaluate the reliability of different 2D and 3D optical routers and network-on-chip architectures in different data traffic patterns. The simulation results depict that Mesh topology improves the reliability parameter by about 5.2% compared to Torus in the same size and traffic patterns. Also, it can be concluded that Crux and DIPU routers are more reliable than the other 2D and 3D state-of-the-art optical routers.
引用
收藏
页数:13
相关论文
共 50 条
  • [31] Design and integration: Chip- and system-level challenges
    Bose, P
    IEEE MICRO, 2003, 23 (03) : 5 - 5
  • [32] Custom Test Chip for System-level ESD Investigations
    Thomson, Nicholas
    Xiu, Yang
    Mertens, Robert
    Keel, Min-Sun
    Rosenbaum, Elyse
    2014 36TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2014,
  • [33] System-level plans for one-chip universes ...
    不详
    COMPUTER DESIGN, 1997, 36 (12): : 52 - 52
  • [34] System-level modeling and performance evaluation of multistage optical network on chips (MONoCs)
    Bai, Luying
    Gu, Huaxi
    Chen, Yawen
    Zhang, Haibo
    Xu, Xinyao
    Yang, Yintang
    PHOTONIC NETWORK COMMUNICATIONS, 2017, 34 (01) : 25 - 33
  • [35] System-Level Impact of Chip-Level Failure Mechanisms and Screens
    Gattiker, Anne
    2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2010, : 173 - 176
  • [36] System-level modeling and performance evaluation of multistage optical network on chips (MONoCs)
    Luying Bai
    Huaxi Gu
    Yawen Chen
    Haibo Zhang
    Xinyao Xu
    Yintang Yang
    Photonic Network Communications, 2017, 34 : 25 - 33
  • [37] System-level network simulation for robust centrifugal-microfluidic lab-on-a-chip systems
    Schwarz, I.
    Zehnle, S.
    Hutzenlaub, T.
    Zengerle, R.
    Paust, N.
    LAB ON A CHIP, 2016, 16 (10) : 1873 - 1885
  • [38] New Circuit Topology for System-Level Reliability of GaN
    Lin, Ming-Cheng
    Chang, Wen-Che
    Wu, Haw-Yun
    Lansbergen, Gabriel Petrus
    Kwan, Man-Ho
    Yu, Jiun-Lei
    Wu, Cheng-Pao
    Tsai, Chun-Lin
    Tuan, Hsiao-Chin
    Kalnitsky, Alex
    2019 31ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2019, : 299 - 302
  • [39] SYSTEM-LEVEL RELIABILITY QUALIFICATION OF COMPLEX ELECTRONIC SYSTEMS
    Farley, D.
    Dasgupta, A.
    Al-Bassyiouni, M.
    de Vries, J. W. C.
    IMCE2009: PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION, VOL 5, 2010, : 231 - 237
  • [40] System-Level Modeling and Reliability Analysis of Microprocessor Systems
    Chen, Chang-Chih
    Milor, Linda
    2013 5TH IEEE INTERNATIONAL WORKSHOP ON ADVANCES IN SENSORS AND INTERFACES (IWASI), 2013, : 178 - 183