System-level reliability assessment of optical network on chip

被引:5
|
作者
Baharloo, Mohammad [1 ]
Abdollahi, Meisam [1 ]
Baniasadi, Amirali [1 ]
机构
[1] Univ Victoria, Elect & Comp Engn Dept, Victoria, BC, Canada
关键词
Silicon photonics; Optical Network on Chip; System-level reliability; Markov chain; Reliability Block Diagram; ON-CHIP; COMMUNICATION; SWITCH;
D O I
10.1016/j.micpro.2023.104843
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Optical Network on Chip (ONoC) is now considered a promising alternative to traditional electrical intercon-nects. Meanwhile, several challenges such as temperature and process variations, aging, crosstalk noise, and insertion loss endanger the data transmission reliability of ONoCs. Many investigations have been made to evaluate the effect of these phenomena on ONoC's reliability. However, system-level reliability assessment of ONoCs based on the failure rate of its essential elements has not been considered by the researchers yet. In this paper, we offer a reliability framework to calculate the reliability of micro-ring resonator, optical path, optical router, and optical topology architecture. Moreover, we developed a system-level simulator called Reliability Assessment of Photonic Network-on-Chips (RAP-NoC) to evaluate the reliability of different 2D and 3D optical routers and network-on-chip architectures in different data traffic patterns. The simulation results depict that Mesh topology improves the reliability parameter by about 5.2% compared to Torus in the same size and traffic patterns. Also, it can be concluded that Crux and DIPU routers are more reliable than the other 2D and 3D state-of-the-art optical routers.
引用
收藏
页数:13
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