A system-level simulation environment for system-on-chip design

被引：1

作者：

Schneider, T ^{[1
]}

Mades, J ^{[1
]}

Windisch, A ^{[1
]}

Glesner, M ^{[1
]}

Monjau, D ^{[1
]}

Ecker, W ^{[1
]}

机构：

[1] Tech Univ Darmstadt, Inst Microelect Syst, Darmstadt, Germany

来源：

13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/ASIC.2000.880676

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Th is paper presents a mixed-signal/multi-language simulation environment for the languages VHDL-AMS, Java, and C++. The environment is implemented in Java and based upon a previously developed VHDL-AMS design environment consisting of a compiler an elaborator and a simulator The latter was extended by open object-oriented Java and C++ interfaces towards system-level simulation capabilities. Obviously, this approach lends itself to a VHDL-centric modeling style. However it also results in a well-defined overall simulation semantics based on the proven semantic principles of VHDL-AMS. Moreover the object-oriented Java and C++ interfaces enforce a much better language modeling style than traditional callback-based procedural language interfaces. The presented open architecture provides good capabilities for research in the field of system-level simulation.

引用

页码：58 / 62

页数：5

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