THE RESEARCH OF TERNARY D-TYPE EDGE-TRIGGERED FLIP-FLOP

被引:0
|
作者
吴训威
陈偕雄
机构
[1] Department of Physics
[2] Hangzhou University
关键词
THE RESEARCH OF TERNARY D-TYPE EDGE-TRIGGERED FLIP-FLOP;
D O I
暂无
中图分类号
学科分类号
摘要
Based upon a previous work, this note proposes a logical design of the ternary D-type edge-triggered flip-flop with triple-rail outputs by inducing the design idea of the binary D-type edge-triggered flip-flop.
引用
下载
收藏
页码:1060 / 1064
页数:5
相关论文
共 50 条
  • [1] THE RESEARCH OF TERNARY D-TYPE EDGE-TRIGGERED FLIP-FLOP
    WU, XW
    CHEN, XI
    KEXUE TONGBAO, 1987, 32 (15): : 1060 - 1064
  • [2] RESEARCH INTO TERNARY EDGE-TRIGGERED JKL FLIP-FLOP
    吴浩敏
    庄南
    Journal of Electronics(China), 1991, (03) : 268 - 275
  • [3] THE SUPPLEMENTARY RESEARCH IN TERNARY EDGE-TRIGGERED FLIP-FLOP
    庄南
    Science Bulletin, 1988, (22) : 1896 - 1899
  • [4] THE SUPPLEMENTARY RESEARCH IN TERNARY EDGE-TRIGGERED FLIP-FLOP
    ZHUANG, N
    KEXUE TONGBAO, 1988, 33 (22): : 1896 - 1899
  • [5] Novel CMOS ternary edge-triggered flip-flop
    Wu, Xunwei
    Wei, Jian
    Wang, Pengjun
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2000, 28 (09): : 126 - 127
  • [6] SPARE GATES FORM EDGE-TRIGGERED FLIP-FLOP
    CAO, VB
    BROWN, B
    EDN, 1995, 40 (06) : 43 - 43
  • [7] CMOS edge-triggered flip-flop using one latch
    Wu, X
    Wei, J
    ELECTRONICS LETTERS, 1998, 34 (16) : 1581 - 1582
  • [8] Differential CMOS edge-triggered flip-flop with clock-gating
    Xia, Y
    Almaini, AEA
    ELECTRONICS LETTERS, 2002, 38 (01) : 9 - 11
  • [9] Differential CMOS edge-triggered flip-flop based on clock racing
    Moisiadis, Y
    Bouras, I
    ELECTRONICS LETTERS, 2000, 36 (12) : 1012 - 1013
  • [10] Flow through latch and edge-triggered flip-flop hybrid elements
    Partovi, H
    Burd, R
    Salim, U
    Weber, F
    DiGregorio, L
    Draper, D
    1996 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 1996, 39 : 138 - 139