Novel CMOS ternary edge-triggered flip-flop

被引：0
|
作者：
Wu, Xunwei [1 ]
Wei, Jian [1 ]
Wang, Pengjun [1 ]
机构：
[1] Ningbo Univ, Ningbo, China
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2000年 / 28卷 / 09期
关键词：
CMOS integrated circuits - Electric losses - Energy dissipation - Logic design - Simulation;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The narrow pulse produced by the race-hazard of clock is used to control the ternary latch, so as to meet the `non-transparent' demand. Based on it, a CMOS D-type ternary edge-triggered flip-flop is proposed. This design is proved to have an exact logic function by PSPICE simulation, and it has a simple construction and lower power dissipation at the same time.
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页码：126 / 127
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