Metastable Electron Traps in Modified Silicon-on-Insulator Wafer

被引：0
|
作者：
戴丽华 [1 ,2 ]
毕大炜 [1 ]
张正选 [1 ]
解鑫 [1 ,2 ]
胡志远 [1 ]
黄辉祥 [3 ]
邹世昌 [1 ]
机构：
[1] State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
[2] University of Chinese Academy of Sciences
[3] Information Engineering College, Jimei University
来源：
Chinese Physics Letters | 2018年 / 05期
基金：
中国国家自然科学基金;
关键词：
SOI; Si; Metastable Electron Traps in Modified Silicon-on-Insulator Wafer;
D O I：
暂无
中图分类号：
TN304.12 [];
学科分类号：
0805 ; 080501 ; 080502 ; 080903 ;
摘要：
We perform the total ionizing radiation and electrical stress experiments to investigate the electrical characteristics of the modified silicon-on-insulator(SOI) wafers under different Si ion implantation conditions. It is confirmed that Si implantation into the buried oxide can create deep electron traps with large capture cross section to effectively improve the antiradiation capability of the SOI device. It is first proposed that the metastable electron traps accompanied with Si implantation can be avoided by adjusting the peak location of the Si implantation reasonably.
引用
收藏
页码：91 / 94
页数：4
相关论文
共 50 条
  • [21] Ultrathin Silicon-on-Insulator (SOI) wafer for compliant substrate
    Noh, Shinyoung
    Ho-Baillie, Anita
    Bremner, Stephen
    Green, Martin A.
    Hao, Xiaojing
    2017 IEEE 44TH PHOTOVOLTAIC SPECIALIST CONFERENCE (PVSC), 2017, : 858 - 860
  • [22] Electron transport in silicon-on-insulator devices
    Gámiz, F
    Roldán, JB
    López-Villanueva, JA
    Cartujo-Cassinello, P
    Carceller, JE
    Cartujo, P
    Jiménez-Molinos, F
    SOLID-STATE ELECTRONICS, 2001, 45 (04) : 613 - 620
  • [23] Electron transport in silicon-on-insulator nanodevices
    Gamiz, F.
    Godoy, A.
    Sampedro, C.
    NANOSCALED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND DEVICES, 2007, : 303 - +
  • [24] VLS growth of silicon whiskers on a patterned silicon-on-insulator (SOI) wafer
    Denki Kagaku Kogyo K.K., Tokyo, Japan
    J Cryst Growth, 1-2 (37-41):
  • [25] VLS growth of silicon whiskers on a patterned silicon-on-insulator (SOI) wafer
    Okajima, Y
    Amemiya, M
    Kato, K
    Asai, S
    JOURNAL OF CRYSTAL GROWTH, 1996, 165 (1-2) : 37 - 41
  • [26] Back-channel-type scanning charge pumping method for characterization of interface traps in silicon-on-insulator wafer
    Yoshida, H
    Sasakura, H
    Yabuuchi, T
    Takami, T
    Uchihashi, T
    Kishino, S
    APPLIED PHYSICS LETTERS, 2001, 79 (12) : 1825 - 1827
  • [27] Design and simulation of a digital optoelectronic switch on silicon-on-insulator wafer
    Tsao, SL
    Tine, ZH
    DESIGN, MANUFACTURING, AND TESTING OF PLANAR OPTICAL WAVEGUIDE DEVICES, 2001, 4439 : 1 - 9
  • [28] Fabrication and characterization of a nanogap edge emitter with a silicon-on-insulator wafer
    Fujii, H.
    Kanemaru, S.
    Hiroshima, H.
    Gorwadkar, S.M.
    Matsukawa, T.
    Itoh, J.
    Applied Surface Science, 1999, 146 (01): : 203 - 208
  • [29] Fabrication and characterization of a nanogap edge emitter with a silicon-on-insulator wafer
    Fujii, H
    Kanemaru, S
    Hiroshima, H
    Gorwadkar, SM
    Matsukawa, T
    Itoh, J
    APPLIED SURFACE SCIENCE, 1999, 146 (1-4) : 203 - 208
  • [30] ION MIXING ENHANCED WAFER BONDING FOR SILICON-ON-INSULATOR STRUCTURES
    KHANH, NQ
    FRIED, M
    TOTH, A
    GYULAI, J
    PECZ, B
    JOURNAL OF APPLIED PHYSICS, 1992, 72 (12) : 5602 - 5605
12345