Universal GALS Platform and Evaluation Methodology for Networks-on-Chip

被引：0

作者：

林世俊 ^{[1
]}

苏厉 ^{[1
]}

金德鹏 ^{[1
]}

曾烈光 ^{[1
]}

机构：

[1] State Key Laboratory on Microwave and Digital Communication,Department of Electronic Engineering,Tsinghua University

来源：

TsinghuaScienceandTechnology | 2009年 / 14卷 / 02期

基金：

中国国家自然科学基金;

关键词：

network-on-chip(NoC); globally-asynchronous locally-synchronous(GALS); wormhole; evaluation methodology;

D O I：

暂无

中图分类号：

TN47 [大规模集成电路、超大规模集成电路];

学科分类号：

080903 ; 1401 ;

摘要：

A networks-on-chip(NoC)cost-effective design method was given based on the globallyasynchronous locally-synchronous(GALS)interconnect structure.In this method,the synchronous mode was used to transmit data among routers,network interface(NI),and intellectual property(IP)via a synchronous circuit.Compared with traditional methods of implementing GALS,this method greatly reduces the transmission latency and is compatible with existing very large scale integration(VLSI)design tools.The platform designed based on the method can support two kinds of packetizing mechanisms,any topology, several kinds of traffic,and many configurable parameters such as the number of virtual channels,thus the platform is universal.An NoC evaluation methodology is given with a case study showing that the platform and evaluation methodology work well.

引用

页码：176 / 182

页数：7

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