Parallel-pipelined Architecture of H.264 Deblocking Filter with Adaptive Dynamic Power

In H.264,the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper,a pipelined VLSI architecture of deblocking filter with adaptive dynamic power is proposed. It avoids redundant computations and memory access by precluding the blocks which can be skipped. And the vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result,the dynamic power of the proposed architecture can be reduced (up to about 89%) adaptively for different videos. And the off-chip memory access is improved compared to the previous designs. Moreover,the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV,1920× 1080 pixel/frame,30 frame/s video signals) video operation at 38 MHz,which significantly outperforms the previous designs from 1.25 times to 4.8 times.