Parallel processing architecture of H.264 adaptive deblocking filters

被引:0
|
作者
Hu Wei
Tao Lin
Zheng-hui Lin
机构
[1] Shanghai Jiao Tong University,Department of Electronic Engineering
关键词
Deblocking filter; Adaptive dynamic power; Parallel processing; Pipeline; H.264; TN919.8;
D O I
暂无
中图分类号
学科分类号
摘要
In H.264, computational complexity and memory access of deblocking filters are variable, dependent on video contents. This paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power, which avoids redundant computations and memory accesses by precluding the blocks that can be skipped. The vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result, dynamic power of the proposed architecture can be reduced adaptively (up to about 89%) for different videos, and the off-chip memory access is improved when compared to previous designs. Moreover, the processing capability of the proposed architecture is in particular appropriate for real-time deblocking of high-definition television (HDTV, 1920×1080 pixels/frame, 60 frames/s video signals) video operation at 62 MHz. Using the proposed architecture, power can be reduced by up to about 89% and processing time by from 25% to 81% compared with previous designs.
引用
收藏
页码:1160 / 1168
页数:8
相关论文
共 50 条
  • [2] Parallel processing architecture of H.264 adaptive deblocking filters
    Wei, Hu
    Lin, Tao
    Lin, Zheng-hui
    [J]. JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE A, 2009, 10 (08): : 1160 - 1168
  • [3] Effective parallel processing architecture for deblocking filter in H.264
    Zhao, Yuexi
    Jiang, Anping
    [J]. Beijing Daxue Xuebao (Ziran Kexue Ban)/Acta Scientiarum Naturalium Universitatis Pekinensis, 2007, 43 (05): : 649 - 653
  • [4] Parallel processing for deblocking filter in H.264/AVC
    Chen, CM
    Chen, CH
    [J]. PROCEEDINGS OF THE FOURTH IASTED INTERNATIONAL CONFERENCE ON COMMUNICATIONS, INTERNET, AND INFORMATION TECHNOLOGY, 2005, : 188 - 191
  • [5] Parallel-pipelined Architecture of H.264 Deblocking Filter with Adaptive Dynamic Power
    韦虎
    林涛
    [J]. Journal of Shanghai Jiaotong University(Science), 2010, 15 (02) : 224 - 230
  • [6] Parallel Processing Architecture for H.264 Deblocking Filter on Multi-core Platforms
    Prasad, Durga P.
    Sonachalam, Sekar
    Kunchamwar, Mangesh K.
    Gunupudi, Nageswara Rao
    [J]. IMAGE PROCESSING: ALGORITHMS AND SYSTEMS X AND PARALLEL PROCESSING FOR IMAGING APPLICATIONS II, 2012, 8295
  • [7] A highly parallel architecture for deblocking filter in H.264/AVC
    Li, LF
    Goto, S
    Ikenaga, T
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2005, E88D (07) : 1623 - 1629
  • [8] Parallel-pipelined architecture of H.264 deblocking filter with adaptive dynamic power
    Wei H.
    Lin T.
    [J]. Journal of Shanghai Jiaotong University (Science), 2010, 15 (2) : 224 - 230
  • [9] A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
    Wang, Sung-Wen
    Yang, Shu-Sian
    Chen, Hong-Ming
    Yang, Chia-Lin
    Wu, Ja-Ling
    [J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2009, 57 (02): : 195 - 211
  • [10] A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
    Sung-Wen Wang
    Shu-Sian Yang
    Hong-Ming Chen
    Chia-Lin Yang
    Ja-Ling Wu
    [J]. Journal of Signal Processing Systems, 2009, 57 : 195 - 211