A Dual-Chip Heterogeneous Packaging Power Device By 2.5D Fan-out Panel Level Packaging (2.5D FOPLP)

Compared to wafer level packaging (WLP), the current FOPLP technology has better performance in small area chips such as power devices, sensor chips, and RF chips, with advantages in conductivity, heat dissipation, and cost. At present, the FOPLP technology for single-chip packaging power devices has become relatively mature. The research on the application of existing FOPLP technology in multi-chip heterogeneous packaging power devices is receiving increasing attention. In this article, a dual-chip heterogeneous packaging power device MOSFET & GaN was devised and achieved based on 2.5D FOPLP technology using epoxy molding compound (EMC) dielectric layer instead of silicon interposer. Simultaneously realizing the signal conduction between chips and signal interconnection of the entire device through laser vias based on EMC dielectric layer. Compared to traditional wire bonding, the volume of this device based on FOPLP technology has been reduced by about 40%, the static drain-source on-resistance (RDS(on)) of device based on 2.5D FOPLP technology was reduced by about 10%. Hence, the device based on FOPLP can bring significant improvements in integration, heat dissipation performance, and electrical connection, improving the overall electrical performance of multi-chip heterogeneous packaging power devices.