A low-power SAR ADC with different weighted capacitor array by using merge and split switching technique

This paper explores the use of the split- merge SAR ADC technique in a TSMC 90 nm process. It can reduce the power consumption of capacitor switching compared with the conventional switching method. On this basis, the weighed capacitor array is assigned to reduce the amount of united capacitors and hence reduce the chip area. The overall ADC includes a two-stage bootstrapped sample and hold circuit, a robust arm comparator circuit, a clock generator for distributing clock pulses in the circuit, a voltage generation circuit and other analog circuits, and other digital circuits for SAR logic control. The simulated results show that a 0.5V 500kS/s SAR ADC with 8.847 bits of ENOB and 6.125 fj/convstep of FoM can be achieved in post-layout simulation.