A new reduced switch count symmetrical and asymmetrical modular topology for multilevel inverters

被引：0

作者：

Anusuya M. ^{[1
]}

Geetha R. ^{[2
]}

Ramaswamy M. ^{[2
]}

机构：

[1] Department of Electrical and Electronics Engineering, Annamalai University

[2] Department of Electrical Engineering, Annamalai University, Tamilnadu, Annamalai Nagar

来源：

International Journal of Power Electronics | 2024年 / 19卷 / 02期

关键词：

carrierless PWM; hybrid topology; MLIs; multilevel inverters; reduced count topologies;

D O I：

10.1504/IJPELEC.2024.136563

中图分类号：

学科分类号：

摘要：

The paper proposes two new topologies for single phase multilevel inverters (MLIs) to operate both in the symmetrical and asymmetrical configurations with a view at lowering the number of switching devices in the path for the flow of the current. It involves a mathematical interpretation to determine the magnitude of the voltage sources in an effort to configure the proposed topology in the asymmetrical configuration and obtain higher number of voltage levels. It engages the principles of carrierless pulse width modulation (PWM) for extracting the shape of the output voltage waveform to a nearly sinusoidal form and there by improve the quality of the power delivered to the load. The procedure owes to analyse the operating modes of both the topologies in MATLAB/Simulink platform and includes an experimental prototype to validate the simulation results. Copyright © 2024 Inderscience Enterprises Ltd.

引用

页码：193 / 220

页数：27

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