Reduced carrier PWM scheme with unified logical expressions for reduced switch count multilevel inverters

The significant reduction in switch count of symmetrical/asymmetrical reduced switch count multilevel inverters (RSC-MLI) topologies has modified the operation of inverter such that the conventional carrier-based pulse width modulation (PWM) schemes such as level-shifted PWM and phase-shifted PWM can no more realise them. To control these RSC-MLI topologies, reduced carrier PWM schemes with modified switching logic gained more prominence. These schemes involve suitable logical expressions to realise the switching states of the inverter. However, these logical expressions vary with topological arrangement and number of levels. Moreover, these schemes produce high total harmonic distortion (THD) in line-voltages. Therefore, to improve the line-voltage THD and generalise the switching logic, a modified reduced carrier PWM scheme with unified logical expressions is presented here. The proposed PWM scheme is directly valid for any topology and can be easily scalable to any number of levels in the inverters. To validate the implementation of the proposed PWM to control any RSC-MLI, experimental studies of various asymmetrical RSC-MLI topologies with the proposed PWM scheme are carried out. Further, to verify the superiority of the proposed scheme in terms of THD, complexity, scalability, and computation burden, its performance is compared with carrier-based PWM schemes reported in the literature.