A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches

被引：1
|
作者：
Sengupta, Anirban [1 ]
Anshul, Aditya [1 ]
机构：
[1] Indian Inst Technol Indore, Dept Comp Sci & Engn, Indore 453552, India
来源：
IEEE DESIGN & TEST | 2024年 / 41卷 / 06期
关键词：
Watermarking; Hardware; IP networks; Security; Codes; Dynamic scheduling; Resource management; PROTECTION; CORES;
D O I：
10.1109/MDAT.2024.3435056
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：70 / 83
页数：14
相关论文
共 50 条
  • [1] High-level Synthesis-based Signal Coding
    Dossis, Michael
    Androulidakis, Iosif
    2016 INTERNATIONAL CONFERENCE ON INFORMATION AND DIGITAL TECHNOLOGIES (IDT), 2016, : 90 - 94
  • [2] A Survey of High Level Synthesis Based Hardware Security Approaches for Reusable IP Cores [Feature]
    Anshul, Aditya
    Sengupta, Anirban
    IEEE CIRCUITS AND SYSTEMS MAGAZINE, 2023, 23 (04) : 44 - 62
  • [3] High-level synthesis-based approach for CNN acceleration on FPGA
    Hosseiny, Adib
    Jahanirad, Hadi
    2023 5TH IRANIAN INTERNATIONAL CONFERENCE ON MICROELECTRONICS, IICM, 2023, : 77 - 81
  • [4] High-Level Synthesis-Based Approach for Accelerating Scientific Codes on FPGAs
    Venkatakrishnan, Ramshankar
    Misra, Ashish
    Kindratenko, Volodymyr
    COMPUTING IN SCIENCE & ENGINEERING, 2020, 22 (04) : 104 - 108
  • [5] Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework
    Butt, Shahzad Ahmad
    Mancini, Stephane
    Rousseau, Frederic
    Lavagno, Luciano
    JOURNAL OF ELECTRONIC IMAGING, 2014, 23 (05)
  • [6] High-Level Approaches to Hardware Security: A Tutorial
    Pearce, Hammond
    Karri, Ramesh
    Tan, Benjamin
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2023, 22 (03)
  • [7] Intellectual property protection of IP cores through high-level watermarking
    Castillo, E.
    Meyer-Baese, U.
    Garcia, A.
    Parrilla, L.
    Lloris, A.
    INDEPENDENT COMPONENT ANALYSES, WAVELETS, UNSUPERVISED NANO-BIOMIMETIC SENSORS, AND NEURAL NETWORKS V, 2007, 6576
  • [8] High-level synthesis of nonprogrammable hardware accelerators
    Schreiber, Robert
    Aditya, Shail
    Rau, B. Ramakrishna
    Kathail, Vinod
    Mahlke, Scott
    Abraham, Santosh
    Snider, Greg
    HP Laboratories Technical Report, 2000, (31):
  • [9] High-Level Synthesis versus Hardware Construction
    Kamkin, Alexander
    Chupilko, Mikhail
    Lebedev, Mikhail
    Smolov, Sergey
    Gaydadjiev, Georgi
    2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2023,
  • [10] High-level synthesis of nonprogrammable hardware accelerators
    Schreiber, R
    Aditya, S
    Rau, BR
    Kathail, V
    Mahlke, S
    Abraham, S
    Snider, G
    IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, PROCEEDINGS, 2000, : 113 - 124
12345