Characterization of HfSiAlON/MoAlN PMOSFETs Fabricated by Using a Novel Gate-Last Process

被引:0
|
作者
许高博
徐秋霞
殷华湘
周华杰
杨涛
牛洁斌
贺晓彬
孟令款
余嘉晗
李俊峰
闫江
赵超
陈大鹏
机构
[1] KeyLaboratoryofMicroelectronicsDevices&IntegratedTechnology,InstituteofMicroelectronics,ChineseAcademyofSciences
关键词
D O I
暂无
中图分类号
学科分类号
摘要
We fabricate p-channel metal-oxide-semiconductor-field-effect-transistors(PMOSFETs) with a HfSiAlON/MoAlN gate stack using a novel and practical gate-last process.In the process,SiO2/poly-Si is adopted as the dummy gate stack and replaced by an HfSiAlON/MoAlN gate stack after source/drain formation.Because of the high-k/metalgate stack formation after the 1000°C source/drain ion-implant doping activation,the fabricated PMOSFET has good electrical characteristics.The device's saturation driving current is 2.71 x 10~4 A/μm(VGS = VDS =-1.5 V)and the off-state current is 2.78 x 10~9 A/μm.The subthreshold slope of 105mV/dec(YDS = —1-5 V),drain induced barrier lowering of 80mV/V and Vth of —0.3 V are obtained.The research indicates that the present PMOSFET could be a solution for high performance PMOSFET applications.
引用
收藏
页码:160 / 163
页数:4
相关论文
共 50 条
  • [1] Characterization of HfSiAlON/MoAlN PMOSFETs Fabricated by Using a Novel Gate-Last Process
    Xu Gao-Bo
    Xu Qiu-Xia
    Yin Hua-Xiang
    Zhou Hua-Jie
    Yang Tao
    Niu Jie-Bin
    He Xiao-Bin
    Meng Ling-Kuan
    Yu Jia-Han
    Li Jun-Feng
    Yan Jiang
    Zhao Chao
    Chen Da-Peng
    [J]. CHINESE PHYSICS LETTERS, 2013, 30 (08)
  • [2] A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process
    许高博
    徐秋霞
    殷华湘
    周华杰
    杨涛
    牛洁斌
    余嘉晗
    李俊峰
    赵超
    [J]. Chinese Physics B, 2013, 22 (11) : 540 - 544
  • [3] A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process
    Xu Gao-Bo
    Xu Qiu-Xia
    Yin Hua-Xiang
    Zhou Hua-Jie
    Yang Tao
    Niu Jie-Bin
    Yu Jia-Han
    Li Jun-Feng
    Zhao Chao
    [J]. CHINESE PHYSICS B, 2013, 22 (11)
  • [4] Gate-last MISFET structures and process for characterization of high-k and metal gate MISFETs
    Matsuki, T
    Torii, K
    Maeda, T
    Akasaka, Y
    Hayashi, K
    Kasai, N
    Arikado, T
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2005, E88C (05): : 804 - 810
  • [5] Gate-last MISFET structures and process for high-k and metal gate MISFETs characterization
    Matsuki, T
    Torii, K
    Maeda, T
    Syoji, H
    Kiyono, K
    Akasaka, Y
    Hayashi, K
    Kasai, N
    Arikado, T
    [J]. ICMTS 2004: PROCEEDINGS OF THE 2004 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2004, : 105 - 110
  • [6] Impact of Oxide Trap Passivation by Fluorine on the Low-Frequency Noise Behavior of Gate-Last pMOSFETs
    Simoen, E.
    Veloso, A.
    Horiguchi, N.
    Paraschiv, V.
    Claeys, C.
    [J]. 2013 22ND INTERNATIONAL CONFERENCE ON NOISE AND FLUCTUATIONS (ICNF), 2013,
  • [7] Low-Frequency Noise Assessment of the Oxide Quality of Gate-Last High-k pMOSFETs
    Simoen, E.
    Veloso, A.
    Horiguchi, N.
    Claeys, C.
    [J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (10) : 1366 - 1368
  • [8] Self-aligned Ge nMOSFETs with gate-last process on GeOI platform
    Zhang, Yi
    Han, Genquan
    Liu, Yan
    Liu, Huan
    Li, Jing
    Hao, Yue
    [J]. 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 219 - 221
  • [9] Characterization of Advanced Gate Architecture Stress on 22nm Gate-Last CMOS Device
    Fu, Zuozhen
    Ma, Xiaolong
    Yin, Huaxiang
    [J]. CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012), 2012, 44 (01): : 779 - 784
  • [10] Self-aligned gate-last process for quantum-well on insulator
    Cheng, Qi
    Wang, Zilun
    Shariar, Kazy
    Khandelwal, Sourabh
    Zeng, Yuping
    [J]. MICROELECTRONIC ENGINEERING, 2018, 191 : 42 - 47