Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

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机构：
[1] Katti, R.R.
[2] Zou, D.
[3] Reed, D.
[4] Schipper, D.
[5] Hynes, O.
[6] Shaw, G.
[7] Kaakani, H.
来源：
Katti, R.R. (romney.katti@honeywell.com) | 1600年 / American Institute of Physics Inc.卷 / 93期
关键词：
CMOS integrated circuits - Data storage equipment - Electric currents - Giant magnetoresistance - Switching;
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摘要：
Performance of current-in-plane (CIP) pseudo-spin-valve (PSV) devices on CMOS silicon-on-insulator underlayers was investigated. Reading and writing field for selected devices were shown to be approximately 25%-50% that of unselected devices. It provided a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits.
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