Parameterized hardware libraries for configurable system-on-chip technology

被引：0

作者：

Luk, Wayne ^{[1
]}

Kean, Tom ^{[1
]}

Derbyshire, Arran ^{[1
]}

Gause, Jörn ^{[1
]}

McKeever, Steve ^{[1
]}

Mencer, Oskar ^{[1
]}

Yeow, Allen ^{[1
]}

机构：

[1] Department of Computing, Imperial College, 180 Queens Gate, London SW7 2BZ, United Kingdom

来源：

Canadian Journal of Electrical and Computer Engineering | 2001年 / 26卷 / 3-4期

关键词：

Algorithms - Application specific integrated circuits - Computer hardware - Computer simulation - Cryptography - Field programmable gate arrays - High level languages - Microcontrollers - Polynomials;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Two key components in configurable system-on-chip (CSoC) devices are instruction processors and field-programmable logic. This paper describes a framework, based on the Pebble language, that can be used to produce parameterized hardware libraries. Such libraries facilitate the development of user-defined hardware on the field-programmable logic to enhance the capability of the instruction processors in CSoC designs. Libraries are presented that support parameterization of the amount of pipelining and serialization to provide implementations with different trade-offs in resource usage and performance. These libraries have been developed to meet the requirements in terms of efficiency, validability, and ease of use. A case study involving DES encryption for Triscend E5 devices is presented.

引用

页码：125 / 129

共 50 条

[21] Interface based hardware/software validation of a system-on-chip
Panigrahi, D
Taylor, CN
Dey, S
IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2000, : 53 - 58
[22] A Configurable OFDM Baseband Processor for RF-UOWC System-on-Chip
Adiono, Trio
Setiawan, Erwin
Jonathan, Michael
Mulyawan, Rahmat
Sutisna, Nana
Syafalni, Infall
Popoola, Wasiu O.
2024 ASIA PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE, APSIPA ASC, 2024,
[23] UTSi® CMOS technology for system-on-chip solution
Megahed, M
Burgener, M
Cable, J
Staab, D
Reedy, R
1998 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS: DIGEST OF PAPERS, 1998, : 94 - 99
[24] Network-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware
LeMay, Michael
Gunter, Carl A.
LOGIC, REWRITING, AND CONCURRENCY, 2015, 9200 : 404 - 426
[25] SOICMOS technology for RF system-on-chip applications
Yue, J
Kriz, J
MICROWAVE JOURNAL, 2002, 45 (01) : 104 - +
[26] A Scalable and Configurable Multiprocessor System-on-Chip (MPSoC) Virtual Platform for Hardware and Software Co-design and Co-verification
Wicaksana, Arya
Tang, Chong Ming
Ng, Mow Song
2015 3RD INTERNATIONAL CONFERENCE ON NEW MEDIA STUDIES (CONMEDIA), 2015,
[27] Dynamic hardware-software partitioning on reconfigurable system-on-chip
Waldeck, P
Bergmann, N
3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 102 - 105
[28] Platform Independent GUI for Reconfigurable Ultrasonic System-on-Chip Hardware
Boulet, Clementine
Ricard, Eric Rovira
Gilliland, Spenser
Gonnot, Thomas
Saniie, Jafar
2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY (EIT), 2014, : 298 - 302
[29] Hardware support for real-time reconfigurable system-on-chip
Waldeck, PJ
Bergmann, NW
MICROELECTRONICS: DESIGN, TECHNOLOGY, AND PACKAGING, 2004, 5274 : 464 - 469
[30] System-on-Chip Security Architecture and CAD Framework for Hardware Patch
Nath, Atul Prasad Deb
Ray, Sandip
Basak, Abhishek
Bhunia, Swarup
2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, : 733 - 738

← 1 2 3 4 5 →