Pipelined VLSI architecture for adaptive image compression

被引：0
|
作者：
Acharya, T. [1 ,2 ,4 ,5 ]
Chen, Po-Yueh [3 ]
Jafarkhani, H. [3 ]
机构：
[1] Intel Corporation, 5000 West Chandler Boulevard, Chandler, AZ 85226, United States
[2] Arizona State University, Department of Electrical Engineering, Tempe, AZ 85287, United States
[3] Institute for Systens Research, University of Maryland, College Park, MD 20742, United States
[4] Department of Electronics, Indian Institute of Technology, Kharagpur, India
[5] Institute for Systems Research, Inst. for Advanced Computer Studies, University of Maryland, College Park, MD, United States
来源：
International Journal of Robotics and Automation | 1999年 / 14卷 / 03期
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摘要：
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页码：115 / 123
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