An interleaved/pipelined architecture for adaptive lattice equalizer

It is well known that the convergence of least mean square (LMS) algorithms to the optimum filter coefficients is slow when the input samples are highly correlated. The adaptive lattice algorithm, a technique to overcome the slow LMS convergence problem, was proposed quite some time ago. However, due to its high complexity, it has not been widely implemented in silicon. In this paper we propose an interleaved architecture for implementing this algorithm. The proposed architecture is hardware efficient, including a reduction in the number of dividers from two to one. The hardware implementation of the proposed architecture is presented and its hardware complexity is estimated at the gate level. Without reducing throughput, the hardware complexity of the proposed architecture is approximately 66% that of the conventional adaptive lattice equalizer.