An interleaved/pipelined architecture for adaptive lattice equalizer

被引：0

作者：

Yu, FQ ^{[1
]}

Willson, AN ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Integrated Circuits & Syst Lab, Los Angeles, CA 90095 USA

来源：

PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

It is well known that the convergence of least mean square (LMS) algorithms to the optimum filter coefficients is slow when the input samples are highly correlated. The adaptive lattice algorithm, a technique to overcome the slow LMS convergence problem, was proposed quite some time ago. However, due to its high complexity, it has not been widely implemented in silicon. In this paper we propose an interleaved architecture for implementing this algorithm. The proposed architecture is hardware efficient, including a reduction in the number of dividers from two to one. The hardware implementation of the proposed architecture is presented and its hardware complexity is estimated at the gate level. Without reducing throughput, the hardware complexity of the proposed architecture is approximately 66% that of the conventional adaptive lattice equalizer.

引用

页码：856 / 859

页数：4

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